1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection in semiconductor integrated circuit (IC) devices, and in particular, to a ESD protection circuit and method that utilizes the selective placement of islands to protect selected pins.
2. Background Art
a. NMOS Transistors as ESD Protection Devices
NMOS transistors have been widely used as ESD protection devices. In one application, with the gate connected to the gate-driving signal, the NMOSFET is used as the pull-down device of a CMOS buffer to drive the output voltage. In another application, with the gate electrically coupled to ground, the NMOSFET is used to protect an input pin or power bus during an ESD event.
The ESD protection of an NMOSFET depends heavily on the snap-back phenomenon for conducting large amounts of ESD current between the drain and the source. The snap-back phenomenon can be described as follows. To start, the high electric field at the drain junction causes impact ionization, which generates both minority carriers and majority carriers. The minority carriers flow toward the drain contact and the majority carriers flow toward the substrate/p-well contact causing a local potential build up in the current path in the p-well. When the local substrate potential is 0.7 volts higher than the adjacent n+ source potential, the source junction becomes forward biased. The forward biased source junction injects minority carriers (electrons) into the p-well, and those minority carriers eventually reach the drain junction to further enhance the impact ionization. This creates a continuous loop so that the MOSFET gets into a low impedance (snap back) state to conduct large amounts of ESD current to accomplish the necessary electrostatic discharge protection.
For ESD protection, NMOS drain contacts are typically kept a few microns away from the gate edge. There is a distributed resistance of the n+ drain diffusion that helps the uniformity of the ESD current flow from the NMOS drain contacts to the source. This is because if the ESD transient current starts to localize at a weak spot near a gate edge, the distributed drain resistance helps to raise the potential of adjacent diffusion area. This causes the entire ESD current to swamp in at a localized spot, thereby causing local heating and eventually damages the device. For this reason, the n+ distributed resistance of the drain region helps an entire gate finger to turn on during an ESD event.
b. Silicide-Processed NMOSFETs
In a salicide process, the silicided diffusion causes ESD performance to degrade due to the much-reduced drain sheet resistance (2 to 3 ohms per square). The ESD high voltage travels directly to the gate-diffusion edge and causes localized gate oxide rupture or source-drain shorts before an entire gate finger can be turned on, much less before multiple gate fingers can be turned on. This is important because an entire gate finger being turned on means that ESD current is flowing from the drain to the source through underneath the entire gate finger, which is more effective for ESD protection than if the ESD current only flows through underneath a portion of the gate finger. One known solution is to use a salicide block, but this is inefficient because the process is complex and one extra mask is required.
c. Multi-Gate Fingered NMOSFET
Due to the need to absorb high ESD transient current, an NMOSFET ESD protection device is typically constructed as a multi-gate-finger structure, an example of which is shown in the layout diagrams of FIGS. 1 and 2. FIG. 3 is the equivalent circuit for FIGS. 1 and 2. However, one known problem with the multi-finger structure is that not all the gate fingers might turn on during an ESD event. Specifically, when the first few gate fingers quickly turn on, these turned-on gate fingers may quickly transition into a snap-back low-impedance condition, thereby reducing the drain terminal to source terminal voltage to a transient voltage that is less than the trigger voltage of the NMOS device, which potentially prevents other gate fingers from turning on. Therefore, with only a partial number of gate fingers turned on to absorb the the ESD energy, the size of the NMOSFET is effectively reduced and the ESD performance degrades.
d. Full-Chip ESD Protection Considerations for Single-Supply and Multiple-Supply ICs
ESD protection devices are typically needed to protect input pins, output pins, I/O pins, and power-bus pins in ICs from being damaged by ESD events.
For a multiple-supply (or called xe2x80x9cmulti-supplyxe2x80x9d) IC, there is a further need to place an ESD protection device between different power buses (such as between VDDH=3.3V and VDDL=2.5V buses). In this case, the positive or negative ESD transient pulses can appear at either one of the power-bus pins, so that each of the two diffusion regions of the MOSFET can be either the source side or the drain side. In addition, the transient ESD current can flow in either direction from the first source/drain (S/D) region to the second S/D region, or vice versa.
e. Known Solutions
U.S. Pat. No. 5,721,439 disclosed a MOS transistor structure having a number of isolated islands in the drain diffusion region. The ESD transient current flows around those isolated islands from the drain contacts towards the drain-gate edge, thereby creating a distributed drain resistance effect for improving ESD protection. However, the implementation of these island structures in the diffusion region of a MOS transistor inadvertently adds to the complexity of device modeling. In one aspect, the structure at least partially divides electrical current into diverted paths and the resultant distributed resistance needs to be modeled correctly. In another aspect, there is a change in the associated diffusion-to-substrate capacitance, which affects the device speed performance and needs to be modeled precisely for accurate IC circuit timing/speed simulation. However, the available simulation and modeling tools do not typically address modeling parameters associated with island-like structures such as one with floating poly segments.
Therefore, there is a need to implement the island-like structure in an IC to provide significant improvement in ESD performance while minimizing the complexity of the device modeling.
It is an object of the present invention to provide an ESD protection circuit that overcomes the problems identified above.
It is another object of the present invention to provide an ESD protection circuit that provides improved ESD protection.
It is yet another object of the present invention to provide an ESD protection circuit that minimizes complexity in device modeling.
It is a further object of the present invention to provide an ESD protection circuit that selectively positions its islands to optimize ESD protection.
To accomplish the objectives of the present invention, there is provided a number of different arrangements of island structures for improved ESD protection.
In one aspect, the MOSFET structure provides islands that are selectively positioned among a group of ESD protection devices for protecting the power-bus, input pins, output pins and I/O pins to achieve ESD improvement in a manner which minimizes the complexity of IC simulation and modeling. In one embodiment, island structures are positioned in the drain diffusion region of selected transistors in an ESD protection device, with the other transistors of the ESD protection device being devoid of island structures. In another embodiment, some of the drain regions in the a given transistor can contain island structures, while the other drain regions of the same transistor can be devoid of island structures.
In another aspect, island structures can be positioned in the drain and source diffusion regions of selected transistors in an ESD protection device. As a non-limiting example, a dual-direction MOSFET structure with islands is placed between different power buses for a multi-supply integrated circuit. In one embodiment, the island structure between different power buses for the multi-supply integrated circuit can have aligned gaps between adjacent islands.